1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor dynamic read-and-write memory (hereinafter, abbreviated to "DRAM").
2. Description of the Prior Art
Referring to FIG. 7, when fabricating each of the memory cells of a semiconductor DRAM 3, an isolating region is formed in a semiconductor substrate 11 by a known element isolating process to separate a memory cell area 21 and a peripheral circuit area 31. Transistors 22 and 23 are formed in the memory cell area 21, and then a transistor 32 is formed in the peripheral circuit area 31. Then, a first layer insulating film 13 is formed so as to cover the transistors 22, 23 and 32. A contact hole 14 is formed through the first layer insulating film 13 so as to reach the diffused layer 27 of the transistor 23. A stacked capacitor 41 is formed so as to be connected to the transistor 23 through the contact hole 14. The stacked capacitor 41 is formed by steps of forming a storage node 42, forming a dielectric film by, for example, a chemical vapor deposition process (CVD process), subjecting the dielectric film to photolithographic etching process to form a capacitor dielectric film 44, forming a conductive film, and subjecting the conductive film to a photolithographic etching process to form a plate electrode 43. Then, the surface of the semiconductor DRAM in process is covered with a second layer insulating film 15. A bit contact hole 25 is formed in the memory cell area 21 through the second layer insulating film 15 by a photolithographic etching process so as to reach the diffused layer 28 of the transistors 22 and 23, and then a contact hole 36 is formed in the peripheral circuit area 31 through the second layer insulating film 15 by a photolithographic etching process so as to reach the diffused layer 35 of the transistor 32. Then, insulating films 26 and 37 are formed respectively over the side surfaces of the bit contact hole 25 and the contact hole 36 by a known side surface coating process, plugs 16 are formed in the bit contact hole 25 and the contact hole 36 by a known wiring line forming process, and a bit line 18 is formed on the second layer insulating film 15 so as to be connected to the plugs 16 and 17.
When fabricating the semiconductor DRAM by the foregoing method, the bit contact hole 25 in the memory cell area 21, and the contact hole 36 in the peripheral circuit area 31 must be formed respectively, by different photolithographic etching processes because the plate electrode 43 is formed in the memory cell area 21. If the bit contact hole 25 and the contact hole 36 are formed simultaneously in the memory cell area 21 and the peripheral circuit area 31 by a photolithographic etching process, only the second layer insulating film 15 is etched in the memory cell area 21 because the plate electrode 43 is formed in the memory cell area 21, while both the first layer insulating film 13 and the second layer insulating film 15 are etched in the peripheral circuit area 31. When etching the plate electrode 43 by the next photolithographic etching process, a portion of the semiconductor substrate 11 in the peripheral circuit area 31 is etched because the plate electrode 43 is not formed in the peripheral circuit area 31. Consequently, the contact hole 36 penetrates the diffused region 35 formed in the upper surface of the semiconductor substrate 11. Thus, the conventional method of fabricating a semiconductor DRAM needs two photolithographic etching processes to form the contact hole 36, which is one of the causes limiting the throughput of the semiconductor DRAM fabricating process.